Layout-database file control: the missing link
The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
DFM
The three critical data validation points in a design flow
Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Reliability research helps to create new technologies
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
3DIC technology provides performance boosts
3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
Design space exploration finds hotspots during early process development
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
Three ways to lift productivity during physical verification
How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Catch multi-patterning errors clearly at advanced nodes
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Yield is money – and other truths of diagnosis-driven yield analysis
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
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