ESD

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.

Automating reliability verification with tools that offer packaged checks provides greater consistency and accuracy across an increasingly complex process.

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.

ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.

Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.