A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
The encryption chain for today's highly collaborative designs needs to be managed with care.
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
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