How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
foundry
P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
EDA innovation is the foundation of progress
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
Preparing for success at the next node with Calibre
How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
Adding system-level, post-layout electrical analysis to HDAP design and verification
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
Reliability verification: It’s all about the baseline
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Managing waivers in reliability verification
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Protecting IP in a collaborative signoff environment
The encryption chain for today's highly collaborative designs needs to be managed with care.
DAC 2012: 20(nm) questions
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
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