A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
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