Machine learning overcomes library challenges at the latest process nodes
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
OCV
Validating on-chip variation: Is your library’s LVF data correct?
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
Clock tree synthesis
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
On-chip clock strategies and GALS
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
On-chip variation (OCV)
Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
Confronting chip assembly challenges
Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]
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