Why comprehensive memory layout verification needs automated reliability checks
Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
layout dependent effect (LDE)
How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
How critical area analysis improves yield
CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
Lessons learned in the finFET trenches
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
14nm/16nm processes
The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
End mixed-signal infinite loops with electrically aware design
Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
Catching layout-dependent effects on-the-fly
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
The five key challenges of sub-28nm custom and analog design
The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
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