SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
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