May 30, 2014
'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
May 26, 2014
In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
April 28, 2014
The encryption chain for today's highly collaborative designs needs to be managed with care.
April 3, 2014
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
January 20, 2014
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 13, 2014
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
January 13, 2014
If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
December 9, 2013
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
December 3, 2013
The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.