Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
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