simulation

April 26, 2019
Portable Stimulus - Three Axes of reuse - Featured Image

Focus your use of Portable Stimulus on three key axes

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
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September 20, 2018
SSD controller case study featured image

How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
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July 23, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The budget case for formal verification

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
June 18, 2017

Portable stimulus

Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
July 15, 2016
Hans van der Schoot is a methodologist in the Emulation division of Mentor Graphics

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
February 29, 2016
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

How to expose X-optimism issues in ASIC and FPGA design

Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
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December 9, 2015
Emulation IoT Networking Challenges

Emulation overcomes the five main IoT and networking verification challenges

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.

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