Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
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