Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
Embedded multicore systems require engineers to make choices around the hardware and software architectures, approaches to certification and more. This is a guide to the trade-offs involved and how to best leverage your options.
Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
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