architecture

September 28, 2020
Jeff Hancock is a Senior Product Manager in the Embedded Platform Technology Business Unit of Mentor, A Siemens Business. He oversees the Nucleus and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services.

How to choose between a hypervisor and a multicore framework

And when this key architectural decision might involve combining both depending on your design’s use-case and demands placed upon it.
September 7, 2020
Ashish Darbari is CEO of formal verification consultancy and training provider Axiomise.

Everything you ever wanted to know about RISC-V architectural formal verification

But you were NOT afraid to ask.... It's time for some answers.
September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
January 28, 2019

Emulation for AI: Part Two

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
December 16, 2013

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
January 18, 2013

Get more out of system architectures

This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
Article  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:
May 15, 2012

Decoupled constraint modelling – a design methodology for hard real-time systems on chip

Using UML to define a software-defined modem SoC in terms of decoupled constraints - the order of activities, the timing they have to meet, and the available resources
Article  |  Topics: EDA - DFM  |  Tags: , , , ,
September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
Article  |  Topics: IP - Assembly & Integration, EDA - ESL  |  Tags: , ,
June 1, 2010

Winning the power and temperature battle with ESL exploration

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.
Article  |  Topics: EDA - ESL  |  Tags: ,
December 1, 2009

Overcoming the limitations of data introspection for SystemC

The verification, test and debug of SystemC models can be undertaken at an early stage in the design process. To support these techniques, the SystemC Verification Library uses a concept called data introspection. It lets a library routine extract information from SystemC compound types, or a user-specified composite that is derived from a SystemC type. […]

Article  |  Topics: EDA - ESL  |  Tags: ,

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