DFM

March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
January 19, 2020

How to build your GDS to OASIS conversion flow

Master the three prerequisites of format translation and chose the right one from the various translation strategies.
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October 9, 2019
Dina Medhat - Mentor

An easier way to make reliability rules and checks more consistent

Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
July 27, 2019

Optimize your database with duplicate data deletion

Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
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May 21, 2019
Calibre node introduction feature - May 2019

Preparing for success at the next node with Calibre

How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
April 15, 2019
Critical Area Analysis Feature - Featured Image

How critical area analysis improves yield

CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
March 25, 2019
Voltage-aware DRC featured image

Use evolving DRC to automate high-voltage and multi-power domain verification

Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
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March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
February 8, 2019
Featured image - Layout merging feature

Fast, accurate layout merging for SoC flows

How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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