Tech Design Forums
Technique
Yield
Yield
All
(2)
Articles
(2)
April 26, 2024
PID yield loss countered by path-based antenna verification
Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?
Article | Topics:
Uncategorized
| Tags:
antenna verification
,
DRC
,
PID
,
plasma induced damage
,
Yield
| Organizations:
Siemens EDA
April 15, 2019
How critical area analysis improves yield
CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
Article | Topics:
EDA - DFM
| Tags:
CAA
,
critical area analysis
,
defect density
,
design for yield
,
layout dependent effect (LDE)
,
Yield
| Organizations:
Siemens EDA
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
PLATINUM SPONSORS
View All Sponsors
twitter
facebook
RSS
Tech Design Forum
Log In
Register
Sponsors
Briefing
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page
Search