Everything you ever wanted to know about RISC-V architectural formal verification
But you were NOT afraid to ask.... It's time for some answers.
Synopsys
Covid-19 rings changes for virtual working
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
AI firsts (and more) at America’s SEMICON
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Introduction to the Compute Express Link (CXL) device types
A look at the device types defined by the Compute Express Link (CXL) standard.
Introduction to the Compute Express Link (CXL) protocols
A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
Introducing the Compute Express Link (CXL) standard: the hardware
A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
Getting better results faster with a unified RTL-to-GDSII product
Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Ensuring system-level security of complex SoCs
Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.
Spreading the word on formal in Bangalore
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.