Synopsys

September 18, 2019

Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs

A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: ,   |  Organizations: ,
September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
September 13, 2019

Introduction to the Compute Express Link (CXL) device types

A look at the device types defined by the Compute Express Link (CXL) standard.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations:
September 12, 2019

Introduction to the Compute Express Link (CXL) protocols

A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , , , ,   |  Organizations:
September 11, 2019

Introducing the Compute Express Link (CXL) standard: the hardware

A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations:
September 9, 2019

Getting better results faster with a unified RTL-to-GDSII product

Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
September 3, 2019

Ensuring system-level security of complex SoCs

Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.
August 9, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
April 3, 2019

Understanding DDR SDRAM memory choices

This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations: ,
March 19, 2019

Using advanced IP to build SoCs for hyperscale data centres

SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.
Article  |  Topics: IP - Selection  |  Tags: , , , ,   |  Organizations:

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