SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
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