10nm

March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
December 31, 2018
MBH featured image

Enhanced model-based hinting may be the edge you need below 20nm

A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations: , , , ,
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Article  |  Topics: EDA - DFM, - EDA Topics, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
March 22, 2017
Computational Process Control feature

How Applied Materials and fab partners are harnessing machine learning

The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
November 26, 2015
Cadence mask coloring assistant

Mixed-signal designs prepare for coloring at 10nm

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
October 29, 2015
Innovus chip layout

Cadence’s path to digital implementation on 10nm

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
May 28, 2015

Dynamic power optimization

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
March 26, 2015

A review of model development for 10nm lithography

John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
Article  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations: , ,
May 19, 2014

10nm processes

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.

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