How to optimize productivity and accuracy in IC design and verification flows
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
design rule check
Hit your tapeout schedules with in-design signoff DRC
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
How cloud computing is now delivering efficiencies for IC design
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
An easier way to make reliability rules and checks more consistent
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
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