DFM

January 16, 2012

Double patterning for sub-28nm ICs

Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.
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October 19, 2011

Plan for 450mm or pay the price

The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
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August 25, 2011

Selective CVD growth of germanium-tin: a new approach for implementing stress in germanium-based MOSFETs

Belgian research institute Imec describes, for the first time, the selective chemical vapor deposition (CVD) of germanium-tin (GeSn) in a production-like environment using commercially available Ge and Sn precursors. The resulting GeSn layers with 8% Sn are defect free, fully strained and thermally stable for temperatures up to 500°C. The technique is used to implement [...]
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August 23, 2011

Quantifying returns on litho-friendly design

By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
June 20, 2011

Foundry overcapacity – yes, it could happen

Current shortages could switch in key markets by the end of the year.
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June 2, 2011

DRC+: a pattern-based approach to physical verification

DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then, the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents [...]
June 1, 2011

Balancing devices and manufacturing

Fab owners are looking to bring down their energy consumption to match the greening of semiconductors themselves.
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February 25, 2011

The fundamental question

Nanotechnology's economic potential will only be harnessed through more basic research, according to a new report from the NSF. Paul Dempsey reports.
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February 25, 2011

The waiting game

As part of our nanotechnology focus, we look at the prospects for graphene and carbon nanotubes in electronics. Paul Dempsey reports.
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December 14, 2010

The player

Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.
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