A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
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