A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
How Chips&Media used HLS on the development of a computer vision IP block.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Using specialised processors to implement key AI computation tasks such as CNNs.
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