August 3, 2022
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
June 28, 2022
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
May 23, 2022
Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
May 5, 2022
DAC returns to San Francisco in July for its 59th year as a purely in-person event.
April 29, 2022
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
April 28, 2022
DVCon Europe will be held as a live event in Munich in early December.
April 28, 2022
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
October 13, 2021
DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.
August 23, 2021
Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.