April 17, 2023
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
April 17, 2023
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
March 30, 2023
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
January 18, 2023
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
January 6, 2023
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
November 21, 2022
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
October 25, 2022
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
August 3, 2022
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
June 28, 2022
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.