Siemens EDA

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.

Siemens PLM strategy VP Stefan Jockusch will keynote on digital twins in the automotive sector at next month's conference in Shanghai.

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.

The trend toward Level 5 fully autonomous vehicles poses major complexity, cost and change issues that Generative Design flows aim to address.

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.

Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?

The company will share a stand at EmbeddedWorld in Nuremberg with its sister Siemens division Polarion and has seven papers across the technical program.

The suite is based on Debian and aims to offer the performance and configurability needed for robust and scaleable enterprise-class applications in medical, industrial, aerospace and defense markets.

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.