DVCon China 2019 preview: Mentor

By Paul Dempsey |  No Comments  |  Posted: March 27, 2019
Topics/Categories: Blog - EDA, - Verification  |  Tags: , , , , ,  | Organizations: ,

Mentor, a Siemens business, will exhibit on Booth #103 at the 2019 edition of DVCon China, taking place on Wednesday, April 17 at the Crowne Plaza Hotel in Shanghai’s Century Park district. The company also features widely throughout the program.

DVCon China Mentor keynote

Driving Digitalization with a Boundary Free Innovation Platform

9:15am – 9:45am, Ballroom A & B

Stefan Jockusch, VP of Strategy, Siemens PLM Software

The keynote will explore the growing need for deep virtualization via the concept of the ‘digital twin’, and how its implications and implementation are illustrated by markets such as autonomous driving and the broader Internet of Things: “The boundaries between the design process of mechanical parts, electronics, embedded software, sensors and specialized IC and sensor technology are disappearing.”

DVCon China Mentor tutorial

Next Gen System Design and Verification for Transportation

4:30pm – 6:00pm, Ballroom A

Increased intelligence and autonomy of next-generation transportation products are driving the ICs behind them to become some of the most advanced semiconductor products. This is disrupting design, verification and development. This tutorial will demonstrate how to use next-generation IC development practices to build and validate the smarter, safer ICs being demanded by transportation products:

  • How can you use High-Level Synthesis (HLS) to accelerate the design of smarter ICs?
  • How should you use emulation to provide a digital twin validation platform beyond just the IC?
  • How do you develop functionally safe ICs?

DVCon China Mentor technical papers

Session: UVM and applications of the new Portable Stimulus Standard

11:15am – 12:15pm, Ballroom A

What Happened to UVM Express?

UVM Express was popular a few years ago because of its simplicity and apparent ease of adoption but did not reach its full potential. This paper will explore why, and propose some improvements aiming to increasing adoption.

Results Checking Strategies with Portable Stimulus

The Accellera Portable Stimulus Standard (PSS) includes a specification that defines critical behaviors – called actions – that must be performed by the test and the scheduling/resource constraints between them. Each leaf-level action includes templated or procedural interface code – an ‘exec’ block – that implements the abstract behavior on the desired platform. The paper will discuss how to take advantage of a platform-agnostic results-checking strategy in the abstract PSS specification.

Session: Formal and requirements driven verification methodologies

2:15pm – 3:15pm, Ballroom A

Handling Inconclusive Assertions in Formal with “River Fishing” Techniques

Handling inconclusive assertions in formal verification is one of the significant challenges faced by project teams deploying formal verification on their designs. The paper will describe a new methodology that will improve the initial state for formal verification. ‘River fishing’ is a good metaphor for the process: by identifying good “fishing spots,” we can significantly increase the number of fishes we catch. Instead of using one initial state to start formal verification, we pick out interesting states from functional simulation traces, and start formal verification from those “fishing spots.”

How to Close the Design-Verification Gap with a Requirements-Driven Reset Domain Crossing Methodology

The paper will describe a requirements-driven methodology for the design and verification of RDC paths in real-world SoC designs. It demonstrates the use of requirements specifications in a systematic and repeatable solution that includes a RDC design requirements specification and verification plan, RDC design and verification, and RDC results progress tracking and completion metrics. The RDC design requirements usage improves the design and verification process and creates a systematic approach for designing and verifying the reset architecture.

Session: Applications of Sequential Equivalence Checking

2:15pm – 3:15pm, Pudong

Applications of Sequential Logic Equivalence Checking

The differences between SLEC and traditional LEC will be discussed, as will most common usages of SLEC. These include verifying that a design behaves the same after optimization, that low power clock gating does not break any functions, that bug fixes and ECOs have not injected new bugs, that fault tolerance or safety mechanisms can detect and fix random faults, and ensuring backward compatibility. There will also be tricks and tips on how to use SLEC efficiently and improve SLEC convergence rate.

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