UVM Cookbook released in new edition

By TDF Staff |  No Comments  |  Posted: March 26, 2019
Topics/Categories: Blog - EDA, - Standards, Verification  |  Tags: , , , , , ,  | Organizations:

An updated and revamped edition of the Verification Academy’s online UVM Cookbook has just been posted. The changes bring the Cookbook in-line with the IEEE 1800.2 UVM standard and promote a new ‘emulation-friendly’ testbench architecture.

Following the update, there is now a single recommended UVM testbench architecture stretching across the Cookbook, allied UVM Framework and Mentor’s Questa Verification IP. In the recommended architecture, TB-DUT connections are handled in a more efficient and reusable way for the increasing number of verification flows incorporating emulation..

All OVM content that was previously a prominent part of the Cookbook has been archived. The main architectural change in the new edition is the recommended use of ‘split transactors’ where, instead of a driver/monitor component having a reference to a pin-level SystemVerilog interface, the transactor will have a reference to a ‘BFM interface’ that supports a set of transaction-level methods called from the transactor. The BFM interface will then drive pin-level signals that are connected to the DUT.

This organization enables higher-bandwidth transaction-level communication across the simulation/emulation boundary, with the BFM interface and all other HDL content executing in the emulator and all class-based UVM components executing in the simulator, as is done in the UVM Framework and by Questa VIP components.

Alongside the architectural update and the emulation-friendly additions, other changes in the new edition Cookbook include:

  • An additional ‘UVM Basics’ Introduction
  • A streamlined chapter on ‘Testbench Architecture’
  • Some material has been moved where more appropriate to ‘UVM Basics’
  • A rewritten and streamlined section on ‘DUT-Testbench Connections’
  • An additional chapter on ‘UVM Messaging’
  • An updated chapter on ‘Register Abstraction Layer’ in line with the 1800.2 standard
  • An updated chapter on ‘Testbench Acceleration’
  • An updated chapter on ‘UVM Connect’

There has also been a general tidying up of appendices and the removal of OVM references from the ‘live’ Cookbook.

The new edition is available for immediate download.

Comments are closed.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors