New tools reinvigorate older processes

By Chris Edwards |  No Comments  |  Posted: April 9, 2013
Topics/Categories: Blog - EDA  |  Tags: , , , , , , ,  | Organizations:

A panel session at DATE last year flagged up the way in which tools developed for advanced processes are being applied to older processes. At this year’s conference in Grenoble, France, Synopsys senior vice president and implementation-group general manager Antun Domic talked about the way in which techniques developed for the latest nodes are being rolled back all the way to 180nm.

“People are going to live for a long time with what we call established technology,” says Domic. “And there are very interesting design problems in the established technologies. From a foundry or manufacturing technology, 90nm may be a solved problem. But from the point of view of design it’s a very competitive area. It’s critical for you to win in the marketplace.”

Domic recalls: “We saw one chip being designed at 180nm with 12 different voltage levels. They wanted to save the last milliwatt. Some designs for 180nm you could design it with eight, ten year-old EDA tools. With 12 voltage regions you are not going to make it.

At Synopsys, we are putting an emphasis on making sure that for the advanced techniques that we develop for 20nm technology also apply to 180nm.”

Although the specific process details are quite different, changes made for the latest processes can be used in older technologies. “There are advances in routing that we do in double patterning that bring benefits in density for other nodes,” says Domic.

“We won an important customer in automotive because we could implement double vias efficiently. The issue for them was reliability and double vias help provide that. We had to do some tweaking of the algorithms to accommodate those kinds of request.

Area reduction and reliability

“The emphasis on reducing area is extremely strong. We have to emphasise those things in our tools. Double vias and the number of power lines needed to implement many voltage domains affect your density and routing effectiveness.

“At the time those nodes were most advanced the told would not have been able to that. With these more advanced algorithms we are enabling new applications. We are not the one choosing for you how many voltage domains you use. But if you need ten we can support that. We enable opportunities. If you are not thinking of how to improve your design, your competitor probably is. You don’t have a secure market position just because you are working at 130nm.”

Synopsys is not introducing specialized tools for the older process nodes but, instead, bringing support for more advanced designs on older nodes into the standard suite. “That resonates well with some customers. If you tell a person that the tool only goes to 90nm it feels as though you will ask them to make a big change later. That’s why we are not thinking of different tools but targeting the same tools to different applications.”

The work from 2.5D and 3D packaging technologies also feeds back. “We built a specialist router for interposers. That router does 45°, for example. It is being used now to do the top layer of metal where you are putting bumps in the middle of the chip. I was pleasantly surprised to find a medical device company using 45° routing in middle of their chip because they needed a very small form factor.

“We are trying to leverage technology for applications that we may not have thought were targets.”

This is the second part of an interview at DATE. We published the first part in March.

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