DAC 2016 preview: Real Intent

By TDF Staff |  1 Comment  |  Posted: May 25, 2016
Topics/Categories: Conferences, RTL, Verification  |  Tags: , ,  | Organizations:

Functional verification specialist Real Intent (Booth #527) will be exhibiting the latest additions and innovations to its Ascent and Meridian product families at the 2016 Design Automation Conference (June 5-9) in Austin, Texas.

Perhaps equally important for foot-weary DAC 2016 attendees, the company will also be offering much-needed caffeine fixes on its stand under the ‘Espresso Yourself’ banner from a high-performance DeLonghi Magnifica.

But to the real business at hand, Real Intent will be offering by-appointment technical presentations on its latest RTL verification and sign-off capabilities for giga-scale SoCs and FPGAs. Click here to book an appointment.

CTO Pranav Ashar will also join colleagues from IBM Research, Mentor Graphics, Paradigm Works and Stanford University on the DAC 2106 technical panel, What is the Real Cost of Verification(Thursday June 9, 3.30PM, Room 18AB). Their discussion will dig beyond dollars and cents to also consider how to measure and improve verification coverage, reduce rework, and improve the chances of first-time silicon success.

 

One Response to DAC 2016 preview: Real Intent

  1. Pingback: Real Intent adds untimed paths to Meridian Constraints

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