Arm Cortex-A processor team focuses on formal
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
Chipmaker
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Arm adds tamper resistance to M-series core
Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
DAC keynotes and sessions aim for AI
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Layout schema generation speeds early-stage yield learning
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
Xilinx plans reconfigurable compute for 7nm FPGA generation
Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.