Cortus adds hardware floating point to low-area processor family

By Chris Edwards |  No Comments  |  Posted: December 10, 2015
Topics/Categories: Blog - Embedded, IP  |  Tags: , , , , , ,  | Organizations:

Cortus has added to its version 2 architecture a processor that offers hardware support for floating-point code.

“With version 2 We wanted to offer a range and tradeoff in computational performance,” said Roddy Urquhart, vice president of sales and marketing at Cortus. “With the FPS26 we are offering a core that’s bigger than the ones we offered previously, extending our range upwards.

“The motivation for developing the FPS26 is certain use-cases for embedded systems or connected intelligent devices. Where you’ve got control systems that benefit from using floating point or where the algorithms suffer from scaling and dynamic range issues,” Urquhart said. “Many motor control and power control systems tend to work better with floating point than with integer where they can face problems with insufficient word length, resulting in underflow or overflow.

Architectural diagram of the Cortus FPS26

Image Architectural diagram of the Cortus FPS26

“We are also seeing interest in floating point in wireless applications, particularly in multi-antenna MIMO systems, which have algorithms that require matrix inversions. You can have scaling issues that are easier to deal with if you have floating-point support.”

Urquhart said the cores in the family are designed so they can be used in symmetric or asymmetric processing combinations. In common with the APS25 launched October 2014, the FPS26 is designed to for a low gate count, supporting a Harvard architecture, sixteen 32bit registers and a five-stage pipeline. On a 90nm process, the addition of floating point approximately doubles the silicon area of the APS25 from 0.099mm2 to 0.192mm2, but delivers almost ten times better performance on floating-point code measured using the Linpack benchmark.

At the software level, the floating-point unit is compatible with the IEEE 754 standard. It performs operations such as addition, subtraction, multiplication and format conversion in hardware with less commonly used operations using software emulation based on code generated by the compiler. C code that uses floating-point datatypes will run on any of the cores in the family, with the compiler generating either hardware floating-point instructions or integer-based emulations depends on which core is the target. “This approach provides more bang for the buck that minimizes silicon area,” Urquhart said.

Version 2 in production

The first company to go public with its use of a Cortus v2 core – in this case the integer-only, three-stage pipelined APS23 – is Synic Solution of South Korea, putting the processor into a cryptographic controller for smartcards that comply with the EMV4.1 standard.

Using the standard APS23 core, the company developed its own security module to detect tampering by hardware hackers as well as an on-chip clock generator to reduce the device’s susceptibility to attacks based on clock glitches and cycle stretching. The device started sampling in late summer but has now moved to volume production.

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