UltraSoC plans to support the RISC-V open-source instruction architecture (ISA) with its debug infrastructure and tools and has lent support to the non-profit RISC-V Foundation.
“RISC-V has attracted the interest of leaders like Google and HP,” said David Kanter of The Microprocessor Report. “The open-source nature of RISC-V is novel, and gives many companies a new opportunity to innovate with specialized hardware components for emerging applications. As with any processor architecture, the RISC-V ISA needs many complementary software and hardware elements to create a full solution. Advanced, vendor-neutral development, debug and analytics support is essential. As such, the participation of specialist firms like UltraSoC is an important step for the RISC-V community”.
Rick O’Connor, executive director of the RISC V Foundation, said: “We are delighted to welcome UltraSoC to the RISC V community. With the Foundation we are building a complete eco-system: end users, processor architects, tools vendors and supporting components. UltraSoC’s debug and development tools will be a great addition to the community.”
UltraSoC aims to provide the RISC-V community with secure, vendor-independent on-chip capabilities to monitor and analyze an SoC’s internal behavior. Seeing RISC-V as the “Linux of the semiconductor industry”, UltraSoC emphasised compatibility with open-source design automation tools such as GDB, as well as a wide variety of commercial third-party products from leaders such as Lauterbach and Teledyne LeCroy.
”We’re delighted to be able to support RISC-V, and we’re committed to doing whatever we can to make it a success,” said Rupert Baines, UltraSoC CEO. “Our stance is vendor neutral and ecosystem based. We aim to create a universal development and debug infrastructure in which designers can freely choose the best architecture for the job – and mix and match their own IP with in-house blocks to create uniquely differentiated products. I believe our approach is an excellent fit with the aims and aspirations of the RISC-V movement.”