Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.

Codasip aims to integrate its Codix-Bk series of RISC-V compliant processor cores with the UltraSoC debug environment.

“Our customers demand more than just traditional processor-based debug in order to meet the needs of the IoT era,” said Karel Masarik, Codasip CEO. “UltraSoC’s broad range of capabilities combined with our commercially proven processor infrastructure, supported on our RISC-V series of Codix-Bk processors, drastically accelerates SoC deployment. We are excited by what this collaboration enables and the benefits it delivers to the new era of RISC-V based SoCs.”

Rupert Baines, CEO of UltraSoC, added: “RISC-V is rapidly becoming an exciting ISA choice for new designs, but suffers from the lack of a proven implementation platform. Combining UltraSoC IP with proven Codix-Bk IP and debug environment results in a powerful SoC debug, analysis and chip-bring up environment that will dramatically accelerate development time while reducing risk for new SoC starts.”