When Cadence Design Systems announced last year that it had worked with ARM and TSMC on delivering the first 20nm Cortex A-15 test chip, the EDA giant picked up kudos. It’s arguably gathered more since with none of its rivals yet having stepped forward to publicly claim a similar feat.
Some of the technology behind that is now coming to market in the new version of Cadence’s Encounter RTL-to-GDSII digital flow which the company formally introduced to users at this week’s CDNLive event in San Jose.
According to Rahul Deokar, product marketing director, the flow is driven by the power-performance-area metric predominant in mobile design and has three new areas of innovation.
GigaOpt addresses the traditional separation between the optimization engines for synthesis and place & route. “We’ve created a common engine to share across the two worlds and that translates into reduced iterations and faster closure,” Deokar said.
Second, CCOpt uses technology Cadence acquired last year with the Cambridge-based start-up Azuro. “Traditionally, you would balance the clocks and than optimize after clock tree synthesis,” explained Deokar. “But today, designs can have 50, maybe 100 clocks, various muxes and gates that are complex, sometimes integrated, then not, then reintegrated.”
The Azuro technology allows for the simultaneous optimization of such a plethora of clocks alongside the physical and logic portions of a design. This lies behind Cadence’s claims on PPA for pre-release projects that Deokar said have reaped results in the range of 10% improvement on performance and power, 30% on clock power and area, and 30% again in IR drop.
The third new headline feature is GigaFlex. This uses abstracted models that can be progressively enhanced over the course of a project to deliver the equivalent of access to a one-billion gate design at the desktop level. Obviously, though, the specification and definition of the model need to be kept consistent, particularly if multiple users are working on a project at the same time. GigaFlex is particularly intended for concurrent top-and-block hierarchical design and implementation.
Added to this are features to address double patterning at 20nm and maintain a correct-by-construction approach that takes intent into account from the beginning of a design and throughout, rather than processing design rule checks after much of the work has been completed.