TSMC Altera heterogeneous integration is cool but is it 3D?

By Paul Dempsey |  3 Comments  |  Posted: March 22, 2012
Topics/Categories: Commentary, Design to Silicon, Blog - EDA, PCB  |  Tags: , ,

The announcement today of the first heterogeneous ‘3D IC test vehicle’ from foundry giant TSMC and one of its main customers, FPGA vendor Altera, is a Biden deal, so it seems a little churlish to split hairs over terminology. But we must.

The vehicle is based on TSMC’s CoWoS (chip-on-wafer-on-substrate) technology, which the company describes as follows:

CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided.

In other words, this is what has hitherto been referred to as ‘silicon interposer’ technology where the various elements in the component system are arranged side-by-side. Also until now, the industry has tended to think of this as 2.5D technology. ‘True 3D’ has typically been considered to be chips stacked on top of one another with through-silicon-vias providing the interconnect – and while it’s been hard enough to do where the parts involved are like-on-like, it’s proving a real slog for unalike-on-unalike.

I’ve never liked ‘2.5D’ as a term and I can fully understand why TSMC wants to be rid of it. It’s always had the pejorative smack of ‘doing things by halves’. In fact, silicon interposer is a an excellent step along the road, a necessary stage in integration. TSMC and Altera deserve kudos here for its first achievement with heterogeneous parts in an environment aimed ultimately at mass production.

We’ve already seen like-with-like interposer implementations, but for Altera this opens up possibilities for FPGA with digital, analog, RF, memory and more within the most tightly integrated environment that looks manufacturably viable in the short-to-medium term. Meanwhile for TSMC, it marks a significant production breakthrough during what has been a difficult period for foundries everywhere.

If we want to go forward to talk about ‘3D interposer’ vs ‘3D TSV’, I can live with that. But you know what would be better still. Let’s kill ‘3D’ altogether. Because I’m wondering whether some of you expected to read about finFETs and ‘3D device structures’ or ‘3D PCB stacking’ or even bad superhero movies when you opened the post. Those have become the most overused two characters in the world.

‘Interposer’ and ‘TSV’ work fine for me solo (though we can’t simply say ‘stacking’ because – brain freezes – that could mean the chip-to-chip ball-based stacking we see in, for example, MEMS way under 1GHz).

All that really matters, as TSMC and Altera have shown, is what you can deliver.

3 Responses to TSMC Altera heterogeneous integration is cool but is it 3D?

  1. Pingback: Synopsys builds 3D into tool portfolio | Tech Design Forums

  2. Desmond Wong on November 4, 2013

    It will take some time to understand what the CoWoS will bring to the industry.
    Although I agree the advantages of WL 3D integration, but it is impossible to truly implement a system super chip without the integration of non-silicon components.

    The key advantage of heterogeneous integration in 3D is to brush up certain system performance which couldn’t achieve at silicon / WL level alone. Take a look at the Telit SE880, the first that a complex RF product design is able to achieve higher sensitivities than the silicon it is based on.

    http://www.businesswire.com/news/home/20121219005045/en/Telits-Jupiter-SE880-Named-2012-Hot-100

  3. Pingback: Intel and Altera extend foundry deal into interposer and full 3D | Tech Design Forum

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