Technical Newsletter #1: Common Platform, Samsung, ARM, Cadence

By Paul Dempsey |  1 Comment  |  Posted: February 29, 2012
Topics/Categories: Blog Topics, Commentary, Conferences, Design to Silicon, Blog - EDA, - General, Newsletters  |  Tags: , , , , , , ,


Welcome to the first Tech Design Forum Technical Newsletter. We’re initially posting these to the site, but they will eventually be emailed exclusively to our registered email subscribers. If you want to make sure you receive them in future, you can register by filling in this form.

Our aim with the newsletters is to deliver short (ish), sharp, pertinent content as well as updates on the latest design guides and technical articles published here. We’ll also be giving email subscribers the first opportunity to suggest topics and questions for our soon-to-be-added Ask the Expert and Round Table Features. But, in timely fashion, this first newsletter concentrates on manufacturing and the surrounding ecosystem.

In about two weeks, the Common Platform foundry alliance (GlobalFoundries, IBM and Samsung) holds both physical and virtual editions of its annual technical conference, the Common Platform Technology Forum 2012. If you’re based in Silicon Valley, you can attend the day-long event on March 14 at the Santa Clara Convention Center.

However, if you are not, a Virtual Technology Forum takes place online, also on March 14, from 9am PT. Registration is now open for both. The virtual forum will be archived for access throughout 2012. The theme for both marks the partnership’s tenth birthday: ‘A decade of invention, a world of solutions’.

We’ve partnered with the Common Platform to produce Q&A interviews and articles that don’t simply preview the forums, but give a more general taste of what foundries and their partners are doing to bring the latest technologies to market.

In this inaugural newsletter, we feature three companies: Common Platform member Samsung along with two of the platform’s leading ecosystem partners, ARM and Cadence Design Systems.

There’s no better way to quiz the Common Platform companies than to attend one of the Technology Forums. But as you read the interviews, your own questions will emerge. So why not send them to us. We’ll pass them on to the interviewees to follow up in a later newsletter. Indeed, we’re eager for your suggestions and feedback on any topics we have covered or should cover. Email us at

In this issue

  • With Mobile World Congress taking place this week in Spain, we get Samsung’s views on design trends in that huge industry, one where it’s a massive player in its own right. Ana Hunter is Vice President of Technology for Samsung Semiconductor, Inc.’s System LSI foundry business. She discusses the silicon going into products today, the options foundries need to offer now and in the future, and how these address mobile’s delicate trade-off between power and performance. Scroll down for our interview with Ana or jump to it.
  • FinFET (aka tri-gate) devices have arrived after years of research. But there’s still confusion as to what they mean for the general user and over what needs to happen to so that designers everywhere can benefit from them. Greg Yeric, ARM Senior Principal Design Engineer, provides an excellent guide to what they do and what you need to watch out for. Scroll down for our interview with Greg or jump to it.
  • Where do 20 and 14nm feature on your roadmap? As Frank Leu, VP Engineering at Cadence, explains, it’s probably time they appeared somewhere. He describes the main challenges ahead and also how the system design ecosystem is collaborating to deliver the necessary support. Scroll down for our interview with Frank or jump to it.

That’s our line-up. Next time, we’ll feature IBM’s views on manufacturing beyond 14nm, GlobalFoundries’ strategy for 28nm, and Mentor Graphics’ approach to the challenges posed by double patterning.

Mobile drives innovation

Ana Hunter, Samsung Semiconductor Inc

Samsung is not just one of the Common Platform foundry members, but also a pioneer in mobile technology for its own products. We spoke to Ana Hunter, Vice President of Technology for Samsung Semiconductor, Inc.’s System LSI foundry business, about trends in that market ahead of next month’s event.

TDF: This week is the Mobile World Congress. How does that and other trends in that market reflect the latest offerings from Common Platform?

Ana Hunter: In Barcelona, we’re seeing many ARM15, ARM9 multicore implementations – dual and quad – using our 32 and 28nm high k-metal gate (HKMG), low power technology. Against 45nm, 32nm HKMG gives about a 30% performance improvement together with about a 40% power reduction. Then, Windows-on-ARM is coming soon and will drive a lot of innovation.

Along side low-power, there are also now demands for low-power, high-performance combinations. With the drive toward tablets and very smart smartphones, designers want more and more performance. We have an LPH process at 28nm that extends the performance capability of the process while maintaining low power, and low leakage SRAM.

Then at 20nm, we offer a single platform technology that has transistor options ranging from very low leakage up to extremely high performance so that designers can achieve very high performance for tablets and smartphones while maintaining battery life.

How are some of the main design challenges working out in mobile and for low power generally?

Multicore is pervasive. I think all our customers are working with some sort of implementation. We support those with many features in the design flow, like dynamic frequency and voltage scaling, adaptive body biasing, thermal management units.

Certainly, there is an important trade off – the more performance, the more leakage. So a big part comes back to offering a wide range of transistors. For example, we have four transistors from ultra high VT to ultra low VT that designers can mix and match to limit leakage in the critical path. We also support nominal VDD and overdrive options. All of these are in the current process.

One interesting development – we’ll talk about it at the forum – is how finFET transistors have huge advantages in improving leakage as you reach 14nm.

The other side of this is innovation in RF, analog and mixed-signal.

Some customers want to integrate more into SoCs; others prefer to optimize individual components. We have to serve both.

For SoC customers, both 28 and 32nm transistors provide excellent RF performance. Standard CMOS logic at both nodes is very good for mixed signal design and we support it in the design kit. Where people want to keep elements separate – and this is not necessarily a Common Platform solution, but is a Samsung one – we are working aggressively on TSVs and 3D ICs.

Ana Hunter will introduce the main Plenary Session at the Common Platform Technology Forum 2012 on March 14.

FinFET for the common man

Dr Greg Yeric, ARM

One of the most hotly anticipated talks at next month’s Common Platform Technology Forum will be given by Greg Yeric, ARM Senior Principal Design Engineer. He will overview work under way to bring foundry access to finFETs. He gave us a primer on this emerging technology.

TDF: What is the big deal about finFETs and what do they mean for IP?

FinFETs hold the promise of being fundamentally better switches than bulk planar transistors. So, they’ll allow favorable power and performance scaling beyond 20nm. However, they are a new kind of transistor with new issues and limitations. They are different enough that one runs the risk of producing sub-optimum IP without good understanding and planning. But properly executed, they’ll mean that 14nm delivers better power and performance.

How big a change are finFETs?

On one hand, they have the same metal-oxide-semiconductor structure, simply folded up, accordion-style, to provide a higher current density. In that sense, designers will see them behave in familiar ways. The key change will be a sizeable bump in the roadmap for some scaling parameters. There’ll be enough notable differences that the transition should offer an opportunity to assess the scaling of our designs.

What specifically should designers be aware of?

Most everyone has heard about quantization – that the finFET drive strength is varied by the number of discrete fins in parallel. For that reason and others, low power designers will face a different granularity in choices than they’ve been used to. Another potentially more interesting side-effect of quantization is a new fin-metal gear ratio. Designers must plan for the fact that finFETs offer a change in the scaling compared to recent nodes. Delay and power can be improved in aggregate, but their components, represented by CV/I and CV^2f, will scale in different ways. I wouldn’t recommend a lazy extrapolation of past trends.

What other differences might there be?

The variability signature will probably change. finFETs improve some aspects of variability but because they have new process components, I’d expect to see other new variation issues. This shift might foretell a change in the balance between local and global variation that will affect memory and logic differently. Also, scaling to 14nm in and of itself won’t be easy, and all of the finFET issues will have to be folded – no pun intended – into this broader context. I’ll discuss a broader process scaling perspective at the forum.

Dr. Greg Yeric will talk on IP Design and the FinFET Transition at the Common Platform Technology Forum 2012. Part of the conference’s Just Over the Horizon – Innovation Pipeline (14nm & beyond) track, the session begins at 3:00pm on March 14 in Great America 1/2/3 at the Santa Clara Convention Center.

Building the platform for 20 and 14nm

Frank Leu, Cadence Design Systems

It’s already time to start thinking about 20 and 14nm, certainly for members of Common Platform’s ecosystem as well as engineers. Cadence Design Systems is one of the biggest of those ecosystem companies. Frank Leu, VP Engineering, set out the key challenges ahead.

TDF: All major players are already driving research to commercialize nodes beyond 28nm. What are the most obvious challenges at 20 and 14nm?

Frank Leu: At the manufacturing end, lithography equipment. On the design side, handling variations is huge. The design cycle must address process, electrical, resistance, timing and power variations and layout-dependent effects (LDEs).

Broadly, what are the options. Which will you address at the forum?

For manufacturing, there’s the dual mask approach. We need double- or even multiple-patterning technology until EUV  technology is ready. And possibly SOI and finFETs/tri-gate. Engineers will have to manage variations and LDEs much earlier in development to accelerate design closure and time-to-tapeout. Delivering big designs with low power and mixed-signal, and thousands of IPs, must also be kept in mind.

Why should engineers start thinking about tomorrow’s nodes today?

The demands for performance and power are there today. You want your mobile phones to be smaller, faster, all that. We need to keep innovating, and 20nm is a paradigm shift – not just on the manufacturing side, but on the design side too. We need to address these challenges now to stay ahead of the curve or we’ll stifle innovation.

How important is integrated ecosystem collaboration in delivering the solutions needed?

Each node transition has brought new technical challenges. With 20nm – and what we’re seeing for 14nm – they require ever increasing collaboration earlier in the development phase, meaning concurrent development of process technology, EDA products and design IP.

In what ways does that collaboration take place within and beyond the Common Platform network?

At Cadence, we’re working more closely than ever with International Semiconductor Development Alliance* companies. That’s the broader R&D grouping that includes all the Common Platform members. Those efforts have been proven on multiple testchips and allow Common Platform itself to offer a design solution that lets fabless companies target advanced nodes. I’ll be talking about this in greater detail at the forum.

* Alongside the Common Platform members, the ISDA also includes Freescale Semiconductor, Infineon Technologies, NEC, STMicroelectronics and Toshiba.

Frank Leu will present on Delivering on 20nm and Embarking on 14nm – Cadence and Common Platform Alliance Partners at the Common Platform Technology Forum 2012. Part of the conference’s Ecosystem track, the session begins at 2:00pm on March 14 in Great America K at the Santa Clara Convention Center.

Now online

That wraps things up for this first newsletter. Thanks for reading. If you’ve arrived here from our email, why not check out some of the latest articles and posts at Tech Design Forum.

Verified RTL to gates: Assertions in aviation hardware development

Verification IP: Synopsys goes 100% SystemVerilog for boost

Printed electronics: EU plastic chips plan

Mobile World Congress: Realizing the shift to LTE

ISSCC: Intel takes considered route to finFET

Guide: Double patterning for sub-28nm ICs

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