FinFETs’ III-V future promises sub-7nm, RF and opto CMOS
FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
Author Archives: Luke Collins
Hybrid chip links ARM core with C-programmable deterministic peripherals
XMOS integrates xCORE configurable, deterministic multicore microcontroller technology with ultra-low-power ARM Cortex-M3 processor to create a low-power ‘programmable system on chip’.
Uptake of formal techniques in verification to be outlined in keynote
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM
TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
Real Intent updates X verification tool
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
SNUG heads to Austin next week
Synopsys user meet in Austin carries forward themes from Boston event.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
SNUG Boston focuses on challenges of gigascale IC design
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
Real Intent links tools to Synopsys flows through in-Sync program
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Synopsys doubles speed of formal ECO checking
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.