Expert Insights - EDA

Anders Nordstrom  |  July 5, 2016

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Anders Nordstrom  |  May 30, 2016

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Andrew Macleod  |  April 26, 2016

Still using Moore’s Law to beat up on the automotive industry?

These days, when it comes to innovation: The car's the star - not the stooge.
Victor Reyes  |  April 14, 2016

Scaling automated software testing with Virtualizer Development Kits

How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
Shenoy Mathew  |  April 13, 2016

The challenge of verifying the evolving Ethernet standard

A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Paul Graykowski  |  April 6, 2016

Accelerating PCIe verification

A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Anders Nordstrom  |  March 1, 2016

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Geoffrey Ying  |  February 10, 2016

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Lauro Rizzatti  |  January 27, 2016

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
Luke Collins  |  January 19, 2016

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors