Expert Insights - EDA

Steve Pateras  |  December 29, 2015

Memory BIST for automotive designs

Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
Topics: EDA - DFT  |  Tags: , , , , ,   |  Organizations:   |  
Bruce McGaughy  |  October 28, 2015

FastSPICE simulators hit their expiration date

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Nasib Naser  |  October 19, 2015

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Amol Herlekar  |  October 8, 2015

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Topics: IP - Design Management, EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Lauro Rizzatti  |  September 12, 2015

Skeet shooting and design debug

In-circuit emulation is attractive but brings with it debug-visibility issues. There are ways to restructure the environment to make bug hunting much more deterministic.
Warren Kurisu  |  August 24, 2015

A scalable RTOS and other essentials for embedded wearables development

The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
Jai Durgam  |  August 19, 2015

Make vs buy in automotive IP

A look at some of the quality and safety requirements that must be met when developing and applying semiconductor IP to the automotive sector.
Topics: IP Topics, IP - Selection, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:   |  
Mick Posner  |  August 4, 2015

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,   |  
Jim Thomas  |  July 10, 2015

What hardware verification can learn from software development

What hardware designers can learn from software verification techniques such as agile, behaviour-driven development, code coverage and zero known defect strategies
Mark Handover  |  June 30, 2015

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  

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