The International Test Conference (ITC) will hold its 50th event from 12 to 14 November in Washington, DC. The conference will celebrate this milestone by including several special events. The conference will also have the usual full technical program, more than 50 posters, as well as a variety of tutorials and workshops. More details of the conference are available here. From a personal point of view…
The most memorable ITC keynote I’ve seen…
…was from Pat Gelsinger of Intel back in 1999. Pat’s keynote pointing out that the capital dollars spent on semiconductor test were staying flat while manufacturing costs were reducing. He warned that by 2012, test costs could equal manufacturing costs if nothing was done. He used his keynote to challenge the test community to solve this problem.
Hoping for similar insights this year, we have tripled the number of executive talks and keynotes in the conference program. There will be six keynote talks from executives, government agencies, and academia spread throughout the conference.
The other highlights from this year’s ITC will include…
…special features to mark the 50th conference year. ITC will be reflecting on test challenges today and the significant impact ITC has had over the past half century. An awards reception on Wednesday will celebrate unique achievements during that time.
Six visionary talks will be presented alongside the keynotes to get perspectives from prominent executives in EDA, ATE, and yield optimization companies. Sky Talks will reflect on the first 25 years of electronics test at ITC, the progress made in the 25 years that have led up to today, and will also offer perspectives and insights into what may happen in the next 25 years.
We’ll have the Global Test Forum, a special village outside the exhibit hall where test technology conferences from around the world will be represented. Each conference will have a representative and monitor to present about their conference, past achievements, and future opportunities.
For the ITC VC Pitch Tank, venture capitalists will form a special panel to review ideas being pitched for funding.
Our exhibits floor will include three teams participating in the Air Force Supply Chain Provenance Challenge and presenting their results. AFRL and AFWERX partnered for this challenge to solve the current microelectronic supply-chain issue. The challenge is to identify solutions that are non-destructive in nature and prove the provenance and suitability for military use of microelectronic parts in commercial-off-the-shelf hardware to be used on base installations or in operation.
Mentor’s plans for ITC include…
…taking a leading role by once again acting as the conference’s premier sponsor, the Diamond Supporter.
On Tuesday, right after the plenary, there will be a Diamond Supporter event, Accelerating Test – Enabling Fast Market Entry and Advanced Automotive Systems. In this session, Mentor partners Infineon and Broadcom will describe the challenges of implementing leading-edge devices and how the Tessent platform enabled them to improve their time to market. The challenge we face today is how to deal with the complexity of huge designs with many blocks and many DFT features. The Tessent platform was designed and built with this in mind. It is one tool and database that manages and shares various DFT feature information (BIST, scan, ATPG, …) and hierarchical data, such that the tool can manage this type of complexity for the user. We are pleased to have NXP discuss “Reducing LBIST Test Time to Meet Functional Safety Requirements for Automotive Microcontrollers” and Broadcom present “Meeting Aggressive TTM Challenges for AI Chips with Advanced DFT Automation” in this event.
Mentor’s executive vice president, Joe Sawicki, will give a visionary talk on Wednesday morning about “Moving from Production Test to Life Cycle Management.”
At the Mentor exhibit booth theater we will host partners who will be able to discuss interesting results and work they are doing with us. This includes AI-DFT, high-speed IO/1149.10, and automotive.
We have ten posters that cover a variety of topics with partners throughout the industry. These posters allow detailed one-on-one discussions with the authors on topics such as AI DFT, optimizing compression, silicon bring-up, HBM, hierarchical test and more.
Mentor’s history with ITC…
…is deep, and we see the conference as an important gathering of industry leaders, a venue for introducing new technologies and sharing significant results. For example, in 2001 we introduced TestKompress at ITC. TestKompress directly addressed and solved the challenge outlined by Intel’s Pat Gelsinger in 1999. It has become the primary technology for semiconductor test for the past two decades and continues to be the core test technology for most of the industry, especially for the newest and most complex devices.
We also used ITC as a primary event for introducing cell-aware test technology and to report the dramatic silicon results that were achieved by prominent semiconductor companies. Cell-aware test was introduced by Mentor a decade ago and is now the plan of record for many leading companies. It is a fundamental technology necessary to reach modern DPPM goals. In recognition of the contribution of cell-aware technology to the industry, Friedrich Hapke of Mentor received the Bob Madge Innovation Award at the 2015 ITC.
You can view all of Mentor’s planned activities for the 50th ITC here.