Tom Anderson |  June 2, 2020
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Lauro Rizzatti |  May 29, 2020
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
Adnan Hamid |  May 6, 2020
How to combine formal and dynamic verification within an app to uncover security vulnerabilities.
Ron Press |  April 24, 2020
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
Adnan Hamid |  February 20, 2020
How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
Tom Anderson |  January 19, 2020
How an integrated design environment can help you overcome complexities within the Universal Verification Methodology and manage the size of the libraries within it.
Jean-Marie Brunet and Lauro Rizzatti |  December 17, 2019
How Siemens PAVE 360 platform leverages emulation to deliver the exhaustive test required for the incoming generation of autonomous vehicles.
Raghav Katoch |  November 22, 2019
A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
Tom Anderson |  November 21, 2019
The vision of portable stimulus is to find a way to write tests that can be portable ‘vertically’ from IP block to subsystem to system, and ‘horizontally’ from simulation to emulation to silicon. However, applying portable stimulus to real chip designs is not trivial.
Ron Press |  November 7, 2019
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?