Toward usable and scalable DFT for 3D IC design
Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Expert Insights - EDA
Executable specifications boost SoC and IP efficiency
Automating executable specifications as they evolve can deliver major efficiencies.
Use digitalization to mitigate the automotive MCU shortage
The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.
Aim for power first for best place-and-route results
The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Advanced symmetry verification is a thing of beauty
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Hit your tapeout schedules with in-design signoff DRC
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
Use machine learning and visualization to accelerate Liberty file verification
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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