Mobile networking and wireless communications are essential technologies. From smartphones to the Internet of things (IoT), we have created an environment that relies on interconnectivity. We effortlessly talk and text around the globe, cars can ‘speak’ to each other to avoid collisions, implanted medical devices monitor and transmit critical health data, and computer games enable tens of thousands of concurrent users worldwide.
These innovations have been made possible by continuing (and significant) evolution in telecommunications, from 3G to 4G to 5G, with the operating frequency band increasing with each new generation. For 5G technology, that frequency range can exceed 40GHz . Ensuring that ICs achieve satisfactory performance in the face of these requirements has given new importance to an otherwise restricted design requirement: Inductance extraction.
Analog and RF ICs form the hardware backbone that supports communication technologies. At high operating frequencies, parasitics can significantly affect the performance of these chips. Specific attention is needed to ensure that analog/RF designs take into account post-layout parasitics to confirm design simulation results match the silicon-fabricated results. Historically, resistance and capacitance parasitics were the main focus for post-layout simulation, while inductance extraction was limited to custom inductor characterization. That can no be longer the case. The increasing impact of inductance parasitics on today’s designs means inductance extraction for interconnect has become essential to ensuring accurate post-layout simulations.
Interconnect parasitics extraction at high frequencies
Interconnects made of a metal conductor and separated by dielectric are not ideal. Signals going through interconnects will always encounter delays caused by material parasitics (consisting of a combination of resistance, capacitance, and inductance parasitics). Resistance parasitics are due to the opposition of electrons passing through the metal, while capacitance parasitics are caused by the electric field between two conductors.
Inductance parasitics are the result of the magnetic field created by passing current through a conductor. Any current passing through a conductor creates a magnetic field. This magnetic field then induces a parasitic current either on the same metal (self-inductance), or on another metal crossing the magnetic field (mutual inductance).
If we focus on resistance and inductance, we can express interconnect impedance as:Where Z is impedance, R is the resistance value (in Ohms), f is the operating frequency, and L is the inductance value (in Henrys). In direct current (DC) and low frequencies, interconnect impedance is dominated by resistance parasitics. However, as the frequency increases, inductive impedance becomes more dominant and affects signal propagation (Figure 1).
Figure 1 Resistive and inductive impedance versus frequency (Mentor)
The ‘skin effect’ is a phenomenon in interconnect parasitics caused by high frequency. As frequency increases, the current distribution is no longer homogenous across the conductor cross-section. The current tends to flow closer to the conductor surface (skin), between the outer surface and a level called the skin depth . This skin depth depends on a combination of the frequency of the current and the electrical and magnetic properties of the conductor depth. It is defined as the depth where the current density is just 1/e (about 37%) of the value at the surface. Figure 2 shows a cross-section view of current distribution in two cases: Low frequency, where skin depth is higher than the conductor width; and high frequency, where skin depth is smaller than the conductor width.
Figure 2 Cross-sectional view of current distribution at low frequency and high frequency, with yellow representing the current flows within the interconnect. At high frequencies, the current flows closer to the conductor surface.
Skin effects increase the resistance parasitics of a conductor at high frequency . They also lead to a frequency-dependent value for the effective inductance and resistance seen by the current. Such effects must be included in the parasitic extraction to achieve accurate results. Figure 3 shows an RLC network for an interconnect in which the frequency-dependent skin effect has been taken into account.
Figure 3 Parasitics modeling for an interconnect, showing the changes due to the skin effect
Inductance parasitics effects
Obviously, the objective of parasitics extraction is to be as accurate as possible compared to physical silicon measurements. Inductance parasitics have several impacts on chip performance. One set of effects appears in long wires (e.g., buses) as changes in delay, ringing (signal oscillation), and overshooting (exceeding target values). Another effect creates reflections in transmission lines due to impedance mismatch . For RF blocks, inductance parasitics can result in reduced gain and bandwidth. For a voltage-controlled oscillator (VCO) design, inductance parasitics can result in drifting of oscillating frequency. Running inductance extraction to account for these impacts during chip design and analysis is extremely important, especially for analog and RF designs that operate at a high frequency.
Inductance parasitics extraction
As stated earlier, inductance parasitics occur due to the magnetic field generated by currents passing through conductors. Accurate inductance extraction faces two main challenges :
- Inductance is a loop phenomenon. Because inductance is a property of current loops, it is difficult to determine which current loops are significant.
- Inductance has a long-range effect. Unlike capacitance extraction, where the electric field is shielded by the conductors (which helps limit the couplings to the closest neighbor), inductance is a long-range effect. The magnetic field is not terminated on neighboring conductors.
There are two principal methodologies for inductance extraction: Loop inductance ; and partial element equivalent circuit (PEEC) .
The loop method is used to compute inductance with return paths, and is typically used for full-chip inductance extraction. Inductance is a property of closed current loops, in which a loop is formed between one net carrying the current (the signal net) and another net carrying the return current in the opposite direction (the return net). In a chip design, power/ground wires carry the return current for signal wires.
The PEEC method is used to compute inductance for a straight wire segment carrying current. Because inductance can only be computed for a closed loop, the current must come back through a return path. Using PEEC, the return path is assumed to be infinitely far away . The advantage of the PEEC method is that it avoids the need to search for all the possible return wires on the chip through which the current might return.
PEEC inductance extraction can be applied on selected critical nets to extract self and mutual inductances for RF and analog designs. It can also be used to extract differential pair nets in designs such as a voltage-controlled oscillator (VCO). Figure 4 shows an RLCK network for signal and ground nets using the PEEC mode, where each net is represented by an inductance value.
Figure 4 PEEC inductance extraction of signal and ground nets
The list of products that depend on high frequency communications is growing rapidly. The success of these products depends on the accuracy and performance of the electronics driving them. While resistance and capacitance parasitics have typically been the main focus for interconnect parasitics extraction, increasing operating frequencies for analog and RF designs now require self and mutual inductance parasitic extraction to ensure accurate circuit performance and high reliability. By including inductance parasitic extraction in the design and verification flow, design companies ensure their ICs will deliver the highest possible level of circuit performance and reliability.
To learn about inductance extraction with the Calibre nmPlatform, download our new whitepaper “Interconnect inductance extraction for analog and RF IC designs”.
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Hossam Sarhan is a technical marketing engineer in the Design to Silicon division of Mentor, a Siemens business, supporting the Calibre PERC reliability platform. His current work focuses on circuit reliability verification and inductance parasitics extraction. Prior to joining Mentor, he worked on modeling and design optimization for on-chip power management circuits. Hossam received his B.Sc. from Alexandria University, Egypt, his M.Sc. degree from Nile University, Egypt, and his Ph.D. from CEA-LETI, Grenoble, France. He may be reached at email@example.com