power intent

May 3, 2021
Static checks May 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
October 16, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Achieving the interactive development of low-power designs

Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:
November 23, 2014
Cadence Palladium cluster

Acceleration homes in on power issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
September 17, 2013

Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design

Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
September 3, 2013

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
June 2, 2013

IEEE 1801-2013 (UPF 2.1)

IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
January 16, 2012

Unified Power Format (UPF)

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.

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