How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
power intent
Achieving the interactive development of low-power designs
Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Acceleration homes in on power issues
Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
Choosing a block representation in a UPF-based hierarchical multi-voltage IC design
This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Formal techniques tackle the SoC verification challenge
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
IEEE 1801-2013 (UPF 2.1)
IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
Unified Power Format (UPF)
The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
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