Achieving more efficient hierarchical DFT for Arm subsystems
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Expert Insights - EDA
Spreading the word on formal in Bangalore
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Correct design and verification coding errors as you type
An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
A new formal proof kit for RISC-V processors
Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
A helping hand for design and verification
Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Speed up design and verification with a smaller layout
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Why hyperlinks are essential for HDL debugging
Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
How emulation’s virtual mode boosts productivity: Part Two
Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
How emulation’s virtual mode boosts productivity: Part One
This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
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