Expert Insights - EDA

Paul Dempsey  |  September 9, 2016

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
Lauro Rizzatti  |  July 22, 2016

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
Hans van der Schoot  |  July 15, 2016

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:   |  
Anders Nordstrom  |  July 5, 2016

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Anders Nordstrom  |  May 30, 2016

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Andrew Macleod  |  April 26, 2016

Still using Moore’s Law to beat up on the automotive industry?

These days, when it comes to innovation: The car's the star - not the stooge.
Victor Reyes  |  April 14, 2016

Scaling automated software testing with Virtualizer Development Kits

How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
Shenoy Mathew  |  April 13, 2016

The challenge of verifying the evolving Ethernet standard

A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Paul Graykowski  |  April 6, 2016

Accelerating PCIe verification

A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Anders Nordstrom  |  March 1, 2016

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  

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