Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
Ashish Darbari describes a formal technique that fuels a rapid, predictable and highly effective methodology.
Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
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