Expert Insights - EDA

The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.

An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

How the digital twin can fuel automotive verification flows impossible in the real world.

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.