Exploiting the power of reset in formal verification
The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Expert Insights - EDA
Speeding AMS verification by easing simulation debug and analysis
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Hardware emulation answers Brooks’ Law
What can you add to a challenging project without pushing out deadlines and muddling communication?
Reachable or reached, covered or coverable – is it just semantics?
How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
2016 – A continuation of change
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
Thought you had verified your SoC? You probably only did half…
Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
2015 – The year in review
Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
Memory BIST for automotive designs
Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
FastSPICE simulators hit their expiration date
Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Ten key tips for effective memory verification
Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
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