Verifying clock domain crossings in UPF-based low-power SoCs
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Expert Insights - EDA
8.8 billion miles to verify
How the digital twin can fuel automotive verification flows impossible in the real world.
An open-source framework for greater flexibility in machine-learning development
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
EUV’s arrival demands a new resolution enhancement flow
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Doc Formal: Achieving exhaustive formal verification of packet-based designs
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Managing waivers in reliability verification
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Doc Formal: The budget case for formal verification
Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Formal fundamentals: what’s hiding behind your constraints
Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
Power analysis isn’t just for battery-operated products
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
How emulation’s SoC and SoS advantages begin with transaction-based co-modeling
An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
PLATINUM SPONSORS
View All Sponsors