Comparing your design to itself – a crucial part of verification
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Expert Insights - EDA
Still using Moore’s Law to beat up on the automotive industry?
These days, when it comes to innovation: The car's the star - not the stooge.
Scaling automated software testing with Virtualizer Development Kits
How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
The challenge of verifying the evolving Ethernet standard
A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.
Accelerating PCIe verification
A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
Exploiting the power of reset in formal verification
The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Speeding AMS verification by easing simulation debug and analysis
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Hardware emulation answers Brooks’ Law
What can you add to a challenging project without pushing out deadlines and muddling communication?
Reachable or reached, covered or coverable – is it just semantics?
How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
2016 – A continuation of change
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
PLATINUM SPONSORS
View All Sponsors