This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
How Chips&Media used HLS on the development of a computer vision IP block.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
How the digital twin can fuel automotive verification flows impossible in the real world.
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