Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
Ashish Darbari sets out the fundamental qualities of a successful formal verification project.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.
Why is formal verification not getting the traction it should. The good doctor has some thoughts on that... and a new solution.
If we thought about verfication-for-security in a different way, the Spectre and Meltdown vulnerabilities could well have been avoided.
Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
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