Expert Insights - EDA

Pranav Ashar  |  August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Jürgen Schloeffel  |  July 3, 2012

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
Topics: EDA - DFT  |  Tags: , , ,   |  Organizations:   |  
Michael Buehler-Garcia  |  June 1, 2012

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:   |  
Jeff Wilson, Mentor Graphics  |  May 22, 2012

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Topics: EDA - DFM  |  Tags: ,   |  Organizations:   |  
Richard Pugh, Mentor Graphics  |  April 25, 2012

No more spaghetti

Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Dennis Brophy, Accellera  |  February 9, 2012

New SystemC reference simulator open for public comment

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.
Topics: EDA - ESL  |  Tags: ,   |  Organizations:   |  

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