Pranav Ashar |  August 23, 2012
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Jürgen Schloeffel |  July 3, 2012
Characterizing standard-cell defect mechanisms helps improve IC testing
Michael Buehler-Garcia |  June 1, 2012
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Jeff Wilson, Mentor Graphics |  May 22, 2012
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Richard Pugh, Mentor Graphics |  April 25, 2012
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
Dennis Brophy, Accellera |  February 9, 2012
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.