layout vs schematic (LVS)

April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , ,   |  Organizations:
November 22, 2019
Raghav Katoch is a product engineer with the Calibre physical verification team at Mentor, a Siemens business.

Improve your LVS debug productivity

A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,
July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
April 14, 2010

Solving the next parasitic extraction challenge

A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]

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