An open-source framework for greater flexibility in machine-learning development
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Intel
Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Introducing Doc Formal: the journey so far
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
The SSD memory revolution
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
How lithography simulations enable silicon photonics
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
Design enablement and entitlement for 14/16nm finFET processes
How EDA tools are evolving to make it possible to design with finFET processes.
Six key criteria for deciding to migrate to a finFET process
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Using standardized design flows to cut time to tape-out – and speed design-flow evolution
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Zeroing in on the problems of fast board-level interconnect
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
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