A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
How EDA tools are evolving to make it possible to design with finFET processes.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
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