How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
Expert Insights - EDA
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
The path to full functional monitoring
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
e language users deserve IDE support too
With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
Not using reliability check waivers? You’re wasting valuable time
Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Extract benefit from the automated refactoring of VHDL code
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
Everything you ever wanted to know about RISC-V architectural formal verification
But you were NOT afraid to ask.... It's time for some answers.
Creating a new paradigm for circuit verification
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
EDA innovation is the foundation of progress
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
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