Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
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