IEDM 2018 aims to span quantum, neuromorphic and CMOS devices
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Blog Topics
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Motion harvester wins MEMS design contest
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
Cadence opens three fronts on mixed-signal failures
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
Arm adds tamper resistance to M-series core
Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Combining tools and services for evolving automotive design flows
Automotive companies need to partner closely with tool suppliers as design processes are disrupted by new technologies.