Blog Topics

What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?

The Electronic System Design Alliance will discuss its recent decision to join SEMI and highlight DAC's new Infrastructure Alley.

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.

Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.