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Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.

Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.